The present invention relates to a method and apparatus for monitoring and controlling processing carried out on a semiconductor substrate, and more particularly for controlling critical dimensions (CDs) of features formed on the semiconductor substrate through feedback and feed-forward of information gathered during in-process inspection of the features. The invention has particular applicability for in-line inspection of semiconductor wafers during manufacture of high-density semiconductor devices with submicron design features.
Current demands for high density and performance associated with ultra large scale integration require submicron features, increased transistor and circuit speeds and improved reliability. Such demands require formation of device features with high precision and uniformity, which in turn necessitates careful process monitoring, including frequent and detailed inspections of the devices while they are still in the form of semiconductor wafers.
One important process requiring careful inspection is photolithography, wherein masks are used to transfer circuitry patterns to semiconductor wafers. Typically, a series of such masks are employed in a preset sequence. Each photolithographic mask includes an intricate set of geometric patterns corresponding to the circuit components to be integrated onto the wafer. Each mask in the series is used to transfer its corresponding pattern onto a photosensitive layer (i.e., a photoresist layer) which has been previously coated on a layer, such as a polysilicon or metal layer, formed on the silicon wafer. The transfer of the mask pattern onto the photoresist layer is conventionally performed by an optical exposure tool such as a scanner or a stepper, which directs light or other radiation through the mask to expose the photoresist. The photoresist is thereafter developed to form a photoresist mask, and the underlying polysilicon or metal layer is selectively etched in accordance with the mask to form features such as lines or gates.
Fabrication of the mask follows a set of predetermined design rules set by processing and design limitations. These design rules define the space tolerance between devices and interconnecting lines and the width of the lines themselves, to ensure that the devices or lines do not overlap or interact with one another in undesirable ways. The design rule limitation is referred to as the critical dimension (xe2x80x9cCDxe2x80x9d), defined as the smallest width of a line or the smallest space between two lines permitted in the fabrication of the device. The CD for most ultra large scale integration applications is on the order of a fraction of a micron.
As design rules shrink and process windows (i.e., the margins for error in processing) become smaller, inspection and measurement of surface featuresxc2x0 CD, as well as their cross-sectional shape (xe2x80x9cprofilexe2x80x9d) are becoming increasingly important. Deviations of a feature""s CD and profile from design dimensions may adversely affect the performance of the finished semiconductor device. Furthermore, the measurement of a feature""s CD and profile may indicate processing problems, such as stepper defocusing or photoresist loss due to over-exposure.
Thus, CD and profile values, and the variation of feature CD from design dimensions, are important indicators of the accuracy and stability of the photoresist and etch processes, and xe2x80x9cCD controlxe2x80x9d to reduce such variation is an important part of semiconductor processing. CD control necessarily involves monitoring and adjusting both the photolithography and etch processes to address CD variations from field to field (FTF) within a wafer, from wafer to wafer (WTW) and from lot to lot (LTL). Among FTF, WTW and LTL variation, FTF and LTL are dominant variation components, while WTW typically counts for less than 10% of the total CD variation. FTF variation is generally determined by process tool performance, such as photoresist coating and baking uniformity, stepper or scanner stage leveling, and etch micro-loading uniformity. On the other hand, LTL variation is generally determined by process stability, including process equipment stability.
Because of the extremely small scale of current CD""s, the instrument of choice for measurement and inspection of surface features produced by photolithographic processing is a scanning electron microscope (SEM) known as a xe2x80x9ccritical dimension scanning electron microscopexe2x80x9d (CD-SEM). Although conventional SEM""s are useful for measuring CD""s, they generally do not provide immediate feedback to the photolithography process to reduce LTL variations. SEM measurement is performed xe2x80x9coff-linexe2x80x9d because it is relatively slow and typically needs to be performed at a separate review station. Consequently, the results of conventional SEM inspections are not typically used to adjust subsequent etch processing; that is, the CD measurement of a particular wafer is not used to decide what etch recipe should be used to process that wafer. Thus, the information gathered from the CD-SEM measurement is not utilized to the fullest extent that will help to improve yield. As a further consequence of the inspection necessarily taking place at a physically separate tool, the wafers must be transferred to and from the tool for every inspection performed. This exposes the wafers to the ambient atmosphere, which can result in unwanted oxidation of the wafer surface or deposition of foreign particles on the surface, thereby lowering yield.
A related process where CD is crucial is known as xe2x80x9cresist trimxe2x80x9d. As those skilled in the art will appreciate, photolithography employing light to expose sub-micron features on a photoresist layer is very costly and complicated. Thus, techniques have been developed to use photolithograpy equipment to expose features that are larger than desired, then follow this exposure with a process called a resist trim to xe2x80x9cshrinkxe2x80x9d the exposed features to their final size. Specifically, after the oversized features are exposed and the photoresist developed, the wafer is brought to an etch chamber, and a specifically designed xe2x80x9cresist etch stepxe2x80x9d is carried out, typically an isotropic etch step that shrinks the size of the developed resist feature. The actual feature (e.g., a polysilicon gate or metal line) is thereafter etched, typically using a different etch recipe in the same or in a different etch chamber.
One method for monitoring and correcting CD variations related to the resist trim process is disclosed in U.S. Pat. No. 5,926,690 to Toprac et al. Toprac teaches selecting one or more test wafers from a lot of wafers whose photoresist has been exposed and developed to create larger-than-desired features, and measuring a representative photoresist feature CD from the test wafers, as with a CD-SEM. The wafers are then processed through a photoresist etch step and a gate etch step, and the CD of the etched feature is measured. The results of the initial and final CD measurements are then used to adjust the etch recipe for the remaining wafers in the lot to drive their CDs to target values. Like other conventional CD monitoring techniques, Toprac teaches measuring CDs of sample wafers (i.e., initially measuring photoresist features formed on the wafers and then measuring gates) off-line at a SEM, and the CD of a particular feature on a wafer is not used to decide what etch recipe is used for processing that wafer.
There exists a need for a simple, cost-effective methodology for fast and meaningful identification and correction of CD variation without significantly reducing production throughput or yield. There also exists a need for a robust and efficient apparatus and methodology for accurately carrying out resist trim operations.
An advantage of the present invention is the ability to reduce CD variations in semiconductor wafers without reducing production throughput or yield, by utilizing information gathered during in-process inspection of the wafers.
According to the present invention, the foregoing and other advantages are achieved in part by an apparatus for processing a semiconductor wafer comprising a measuring tool for imaging the wafer to obtain a data set representative of a CD of a target feature on the wafer; a storage medium that stores a plurality of reference data sets, each reference data set representative of a reference feature CD and associated with a different known set of first process parameter values; a processor configured to identify the reference data set that most closely matches the target feature data set to obtain the first process parameter values for performing a first process on the wafer; a first processing tool for performing the first process on the wafer using the first set of process parameter values; a transfer mechanism for transferring the wafer between the measuring tool and the first processing tool; and a chamber for enclosing the transfer mechanism and allowing communication between the transfer mechanism, the measuring tool and the first processing tool in a clean and controlled environment.
Another aspect of the present invention is that the processor is further configured to select a second set of process parameter values based on the imaging of the target feature CD, and provide the second set of process parameter values to a previously visited processing tool.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only exemplary embodiments of the present invention are shown and described, simply by way of illustration of various modes contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.